DIFFERENCE BETWEEN DIBL AND GIDL.

GIDL:  gate induced drain leakage is a leakage mechanism from the gate-drain overlap region caused when the Drain voltage is very high and Gate voltage is very low.The reverse biased pn junction will undergo band to band tunneling in which the electrons tunnel from the valence band of the n-type tunnel into the conduction band of the p-type and the holes tunnel vice-verse. This results in a leakage current through the gate oxide.

DIBL: Drain induced barrier lowering is related to the reduction in the threshold voltage of the transistor due to the large depletion region created by the Drain potential.U can think of it as-since already a part of the region under the gate is depleted by the drain, only a little amount of gate potential is needed to complete depletion in the rest of the area.This means a lower threshold voltage.

Rectangular FINS VS Triangular FINS

On 23^th April Chipworks posted a blog revealing the inner workings of the Intel 22 nm technology and the architecture of the corresponding FinFETs or, as Intel calls them, tri-gate transistors.

Figs 5, 6 and 7 in the Chipworks posting compare the “unexpected” slope of the fabricated transistors with the original tri-gate schematic shown by Intel last year. There is a lot of speculation about the possible advantages and disadvantages of the trapezoidal (or almost triangular) shaped ‘bulk’ FinFET.

Driven by natural curiosity we decided to shine some light on these questions by doing 3D simulations with our ‘atomisic’ simulatorGARAND, although at this initial stage the ‘atomicity’ doesn’t play any role in our simulations. Fig 1 compares the TEM image of one of the FinFETs from Fig. 7 of the Chipworks posting with our simulation domain. Since we do not have information about the doping distribution in the Intel FinFETs we have assumed a lightly doped channel, which is beneficial from the point of view of statistical variability.

Fig. 1 Comparison of the TEM image of one of the FinFETs from Fig. 6 of the Chipworks blog with the GARAND simulation domain.

The electron concentration and the potential distribution along the fin are illustrated in Fig.2. We have assumed that there is a high doping concentration stopper below the fin in the STI region. Clearly FinFETs are more complicated devices in terms of understanding and visualisation compared to the ‘old’ bulk MOSFETs.

Fig. 2 Electron concentration and the potential distribution along the fin.

The current density distribution across the fin in the middle of the channel at different gate bias conditions is illustrated in Fig. 3 and is rather complex. At low gate voltage the maximum current density is in the middle of the channel where the gate has least control over the turning-off of the device. The depletion region caused by the highly-doped stopper below the channel prevents current flow at the very bottom of the channel – one drawback of the bulk FinFET architecture. At high gate voltage the current moves towards the interface, crowding at the top of the fin due to the focusing gate fringing field there, with quantum mechanical confinement concentrating the charge in a small circular region. Fig. 4 animates the changing gate bias, focussing on the fin channel.

Fig. 3 Current density distribution across the Fin at different gate bias conditions.

Fig. 4. Close-up view of the fin with an animation of the current density with increasing gate bias.

Undoubtedly the result that we found most interesting is the comparison in Fig. 5 between the gate length dependence of the threshold voltage for the trapezoidal Intel transistor and an equivalent rectangular-fin transistor (same fin height and with fin width equal to the average width of the trapezoidal fin). Clearly the rectangular fin has better short channel effects. Still, the million dollar question is if the almost-triangular shape is ‘on purpose’ design, or is this what bulk FinFET technology can achieve in terms of the fin etching?

Fig. 5 Threshold voltage dependence on gate length comparing the Intel-type structure with an ideal rectangular FinFET.

We would be delighted to hear your opinions on this interesting device, particularly with regard to the shape.

9 track cells VS 12 track cells

track is defined as the path in which nets can pass through.

Track is generally used as a unit to define the height of the std cell. a 12 track cell will  be taller than a 9 track cell. a 12 track std cell will be taller , that means more metal 1 routing  space is available within the cell, hence cells will be faster. where as in a 9 track cell, the cell  will be compact, but speed is less compared to 12 track.

9track, less area, less speed compared to 12 track.

12tarck, more area, more speed compared to 9 tracks.

Wide performance range for all types of designs

• Ultra high density/low power; 7 or 8-track (SC7/SC8) libraries for cost critical applications.

• High density; 9 or 10-track (SC9/SC10) libraries for mainstream applications.

• High performance; 12-track (SC12) libraries for speed critical designs.

• Variety of architectures based on different track heights and cell designs cover a wide performance, power and area range.
• High Performance libraries are 20% faster than High Density mainstream libraries
• Ultra High Density versions based on smallest cell height require 20% less area and power than mainstream libraries.

FINFETS

WHY FINFETS

                                        Since the advent of semiconductors and throughout the long history of designing integrated circuits for everything from computer hardware to multifunction mobile devices, the basic tenet of Moore's law has remained the same: the number of transistors on a given area of silicon doubles every two years.

Between the foundries developing advanced process nodes and their consumers' insatiable demand for more functionality, the industry has fulfilled Moore's Law. The transistor count on today's advanced multicore processors is reaching the 3billion range – a long way from the 6800 processor of the mid 1970s that had just 5000 transistors.

Semiconductor manufacturing foundries helped make this growth achievable by introducing smaller geometry cmos process nodes using planar field effect transistor (FET) technology, where the latest node effectively doubled the gate density compared to the previous generation every couple of years. As we approached the sub nanometre range with the 90nm node and beyond, static leakage became an important factor such that while every new process generation may have doubled the gate density, it also doubled the amount of leakage current.

This leakage could be mitigated through the use of high voltage threshold dopants at the expense of device performance, or through the use of advanced design techniques, such as power gating or multivoltage islands. Controlling current leakage when the transistors are switched off is important to preserve battery life or minimise power consumption in computer and mobile applications that spend most of their time in an idle state.

Economics also plays a factor in determining whether to move to advanced processes and when. If chips can take advantage of the increased density to provide more functionality, then it generally made sense to move to the next node, even if mask and process costs were higher. This was the case as designs moved from 65nm to 45/40nm and then again to 28nm. However, the 20nm process node has introduced a new set of challenges, including double patterning and very leaky transistors due to short channel effects. Both are negating the benefits of transistor scaling.

The move from 28nm to 20nm was also unattractive economically for many, since it didn't provide the same level of performance and area gains seen with previous generations. Even with the 30 to 50% density improvement enabled by moving from the 28nm to 20nm process technologies, the performance gain is nowhere near the same as that seen with the move from the 45/40nm to the 28nm process node.

While the planar FET may have reached the end of its scalable lifespan, the semiconductor industry has found an alternative approach with FinFETs; viewed by many as the best choice for next generation advanced processes.

With advanced geometry planar FET technologies, such as 20nm, the source and the drain encroach into the channel, making it easier for leakage current to flow between them and making it very difficult to turn the transistor off completely (see fig 1a). FinFETs are 3d structures that rise above the substrate and resemble a fin, hence the name. The 'fins' form the source and drain, effectively providing more volume than a planar transistor for the same area (see fig 1). The gate wraps around the fin, providing better control of the channel and allowing very little current to leak through the body when the device is in the 'off' state. This, in turn, enables the use of lower threshold voltages and results in better performance and power.



Many semiconductor design companies are moving rapidly to manufacturing their devices on the advanced 16nm and 14nm FinFET based process geometries, simply because the performance and power benefits are compelling. Many test chips have taped out and the results are now starting to come in.

One of the earliest manufacturing providers at the 14nm process node, Samsung has been developing FinFET process technology for several years and is now ready for early adopter production. Samsung's 14nm LPE process is providing almost 150% better performance from a die half the size of the previous node and improving power consumption by around 150% when compared to its 28nm process technology (see fig 2).




From the economic perspective, data from International Business Strategies shows that the move to 20nm and FinFET results in essentially the same cost per die (Q1 2014 estimates), especially as devices increase in size (see fig 3).



FinFET devices can operate from a lower supply voltage than planar transistors since they have a lower threshold voltage. This drop in supply voltage can improve dynamic power consumption significantly: at the least, users can expect a 20% improvement from a drop in supply voltage of just 0.1V and this constitutes a strong driver for FinFET adoption.

Given that the transistors can operate at a much lower voltage than nominal, additional dynamic power savings on that facet alone would be achievable. In addition, foundation library providers are investigating whether or not it makes sense to introduce smaller height standard cells that could reduce dynamic power consumption further.

These providers are likely to release different height libraries, allowing designers to target specific performance or power applications as foundry process design kits are stabilising for production.

FinFET processes are already in production. Intel was one of the first semiconductor manufacturers to use the 22nm node, where it reported power savings of up to 50% when compared to its 32nm process. Semiconductor manufacturers such as TSMC, Samsung Foundry and GlobalFoundries are also moving to production rapidly with several test chips already taped out. But what does it take to move a design to the new FinFET processes and take advantage of the performance and power benefits?

The 20nm process node was necessary to help build the foundation for the advanced FinFET processes. With the smaller device geometries, traditional lithography/optical manufacturing techniques no longer have the required resolution where double patterning – using litho-etch-litho processing – becomes necessary. The number of manufacturing design rules has increased significantly and these have to be handled by various eda tools, such as place and route, physical verification and extraction.

The industry's experience with 20nm has paved the way for an easier transition to FinFET processes. Many of the tool improvements can still be applied, but the handling of FinFETs does require a few more changes; for example, SPICE BSIM-CMG models had to be created to add the 3d effects. It is also true that, with 3d transistors, capacitance becomes a primary concern. EDA tools must build in high resistance interconnect optimisation in order to mitigate these capacitive effects. Layer awareness is also essential to provide optimal metal layer assignment during routing of the design.

Although FinFET processes may seem new, development of the technology itself has been in progress for almost a decade. The industry has worked together to make the shift to an advanced new process node as seamless as possible, with minimal impact to current design methodologies.

Consumer appetite for new functionality remains high and the move to designing with FinFET process technologies will help fill that need and keep Moore's Law very much alive.

Mary Ann White is product marketing director, Galaxy Implementation Platform, for Synopsys.

Author
Mary Ann White

Advanced Clock Tree Synthesis

Reducing Power with Advanced Clock Tree Synthesis:

Clock trees pose a growing challenge to advanced node IC design, particularly with regard to the chip power consumption. Clocks are the single largest source of dynamic power usage, which makes clock tree synthesis (CTS) and optimization as a good place to achieve significant power savings.

In today’s leading-edge designs, CTS is further complicated by two relatively recent developments: the explosion in the number of modes, corners, and power domains across which the clock must operate, and the increasing resistance and variation in resistance between design corners.

It has become essential to have a power-aware, multi-corner multi-mode (MCMM) CTS with smart clock gate handling, slew shaping, register clumping, and other advanced techniques for reducing power, skew, area, and buffer count.

Multiple Modes, Corners, Power Domains Impact Clock Power:

Variability associated with multiple design modes, process corners, and power states makes balancing clocks more challenging than ever. Using a CTS engine that cannot efficiently and accurately represent more than a couple of mode/corner scenarios leads to errors due to multiple manual CTS runs, longer design times, and lost performance and power because of over-buffering and over-margining required when mode/corner/voltage scenarios are processed serially. 

Process Scaling Effects on Clock Power :

At smaller geometries, resistance per unit length of interconnect is rapidly increasing when compared to capacitance, and if not addressed, could impact circuit performance and clock trees. In addition to the increasing resistance, the variation of these values is also increasing.

Low-Power CTS Techniques:

Clock power consumption is a factor of capacitance, switching activity, and wire length. Low-power CTS strategies include lowering overall capacitance and minimizing switching activity. Some of the advanced techniques to help address power, and also timing, are listed below.

• Reducing functional skew and skew across corners by using MCMM CTS
• Lowering leaf cluster capacitance with register clumping and clock gate cloning and de-cloning
• Improving clock gating coverage with netlist-level gating, hierarchical gating and activity based gating
• Minimizing switching activity with smart clock gate placement

WHY SCAN FREQUENCY SHOULD BE LOWER THAN CLOCK FREQUENCY?

why scan frequency should be low?

                During Testing Circuit activity increases during testing and leads to high test power dissipation. i.e

Drop in power supply voltage due to IR drop

Drop in voltage lowers current flowing through transistor

Time taken to charge load capacitor increases.

Causes

  Ground bounce

  Excessive heating ,Permanent damage in circuit

  Good chip labeled bad, unnecessary yield loss

  stuck and delay faults

Clock Speed-Up under Power Constraints

Test clock frequency lowered to reduce power dissipation

Power dissipated in a clock cycle, ½ CV ²œ  (œ= switching power)

Worst case power =½ CV ²œ _{peak    = power budget.}

  F _test <= (2 * powerbudget) / CV ²œ _peak    >=  (½)CV ²œ _peak F _test

If œ =  œ _peak/ I    then    f= i * ftest without exceeding Pbudget

C, V constant for a circuit

Test clock can be increased when switching activity is low

Strong correlation between number of transitions in scan cells and test power dissipation.

Low activity in scan chain => Scan frequency can be increased without exceeding Pbudget .

why clock inverters over clock buffers?

why clock inverters  over clock buffers?

The factors which we consider are the equal rise time  and fall time, drive strength and the insertion delay of the cell. a perfect clock tree is that which have equal rise and fall times with 50% duty cycle for the clock. comparatively clock inverters will have less delay than buffers of same drive strength, also inverters. 

    If we replace a buffer with 2 inverter we can balance the clock rise and fall delay for longer length of the net.  

FD-SOI

Introduction to FD-SOI:

                              Fully-Depleted Silicon On Insulator, FD-SOI, is emerging as a promising  solution to continue the CMOS scaling roadmap at the 22nm technology node and beyond, especially for Low Power and System-on-Chip applications. 

                          Compelling simulation and silicon data for nanometer scale transistors is becoming available. However, as potential users realize the many interests of this technology, the next question is: what about design ? Would a  transition to a Fully-Depleted SOI technology mean a lot of disruption at design level? With FD-SOI processes for the 22nm/20nm CMOS node still in demonstration phase, it is early to give complete answers; on the other hand, this is an important factor in the decision to fully engage in this technology, so it is worth sketching the best picture possible at this stage. This document therefore intends to synthesize what is known or can be most reasonably expected when designing for FD-SOI; it will also indicate some new potentialities opened up by FD-SOI that designers may be able exploit. It builds upon information released in publications such as those listed at the end of  this document or workshops organized by the SOI Consortium.

                          It hopes to demonstrate that a transition to FD-SOI could be, to a large extent, a continuation of current design  practices rather than a revolution, with some added benefits for designers. After a quick overview of the FD-SOI technology and the opportunities it offers, this review will address its impact  on design from System-on-Chip integration level, through complex IP level, down to foundation IP and library design level.

Unique Features of FD-SOI:

Figure shows how a few unique features of FD-SOI namely the absence of channel doping, the ultra-thin body, the resulting excellent electrostatic control of the channel, plus the total substrate isolation enable devices that can be used very advantageously from a design and product perspective for low power System on Chip. 

SHORT CUTS FOR EDITING WIRES IN CADENCE 14.1

Short cuts for editing wires in cadence 14.1

E	Opens or closes the Edit Route form
A	Select
Shift+A	Edit Wire
M	Move Wire
O	Add Via
S	Stretch Wire
Shift+X	Cut Wire
Shift+R	Move/Resize/Reshape (non-connectivity-based move/resize/stretch)
Shift+S	Populates the Edit Route form with net name, width, layers, and shape of highlighted (queried) wire or pin.
P	Toggles to previous object under cursor.
D	Opens or closes the Select/Delete/Deselect Route form
N	Toggles to next object under cursor.
Ctrl+W	Deletes the queried segment or via.
Esc	Removes the entire route.
Number keys	Change the added wire to a specific layer number. If you want the wire to be added to metal layer 1, use the 1 keyboard shortcut, use the 2 keyboard shortcut for metal layer 2, and so forth.
Single-click	Ends the segment, allowing you to continue the route in either the same direction or the orthogonal direction.
Double-click	Ends the route.
D	Changes the added wire to the layer below the current layer.
U	Changes the added wire to the layer above the current layer.

Inputs and Outputs of PD.

Inputs and Outputs at each stage of PD Flow.
Floorplanning:
Inputs:
·    Design Setup
·    Gate Level Netlist
·    Milky way reference Library
·   SDC (Synopsis Design Constraints)
·    TDF (Top Design File)
Outputs:
·         Floorplanned Cell
Checks:
·    Is Macro orientation correct
·    Is placement Legality (i.e. Cell overlaps, cells outside the core boundary ) fine
·   Is Macro placement is according to macro placement guidelines?
·   Placing Macros using Data Flow diagram and by fly-line analysis.

Goal:
·  Goal is to provide continuous area for Standard Cells to be place.
· The Macro plcmt should not lead to Congestion.


Power Planning:
 Inputs:
·         Floor planned Cell
·         Power Budget
·         The top level Engineer may freeze the step , stop, width of Vertical Straps (Because we are designing a block which is going to fit in some chip so the Vertical straps in the chip nd in our block should match, dats the reason In Block level design the top engineer gives us the Vertical straps constraints) {M6pwr.tcl}
Outputs:
·         Power Mesh is Synthesized with IR Drop less than 5 % {VDD+VSS}
·         Floor Planned Cell with Power Mesh
            Checks:
· Check whether u have met the Required IR Drop
· Verify PG connections to check for floating shapes or floating pins  { Power DRC’s }
·Check whether the Placement Legality is fine.

 Goal:
·To meet the Required IR Drop.
If not std cells will not get required power.

 Placement:
 Inputs:
· Floor planned Cell
· Constraints like don’t touch cells (might be already written in SDC ) if not u need to give the cells which u don’t want them to be removed during placement optimization.
· Skew file {in second iteration to meet Timing violations by adding USEFUL SKEW}
Pre requisites for Placement:
·         First of all there should be continuous area for standard cells and the power n/w should be synthesized with the acceptable IR drop.
·        
Checks:
· Check the timing Reports nd analyze them
· Check the Placement Legality
· Check for Global Route Congestion
· Is Std cell Placement Utilization Ok..???

Goal:
· Trying to meet as many setup vio’s as psble.
· Should have acceptable std cell utlzt.
· Should be Congestion Free.

Clock Tree Synthesis:
Inputs:
· Placed Cell
· CTS Constraints
· Non Default Routing Rules {NDR , Bcoz during clock signal (routingclock_route.tcl)Clock nets are largely pruned to Cross Talk effect }

Goal:
·To Balance Insertion Delay
· To make Skew Zero.
For this we this reason we will need to synthesize the clock tree
·After CTS you should meet all the Hold Vio’s.

Checks:
· IS Skew is minimum and Insertion delay balanced.
·IS Timing {Especially Hold} met, if not why?
· If there are timing violations are all the constraints constrained properly.{like not defining false paths, asynchronous paths, multicycle paths}.
· IS std Cell Utilization acceptable at this stage
· Check for Global Route Congestion
· Check for Placement Legality.

GRAPHENE updates by (NTNU) Norway

Mobile phones that bend, self-powered nano devices, new and improved solar cell technology and windows that generate electricity are but a few of the potential products from the union of semiconductors and graphene.

Semiconductors grown on graphene at the Norwegian University of Science and Technology (NTNU) may be the most important research breakthrough of 2012 in Norway. At the centre of the research efforts are Professor Helge Weman, Professor Bjørn-Ove Fimland and post-doctoral fellow Dong Chul Kim. The team is now working on translating the results of their basic research into an initial prototype.

Just one atom thick

In the 1960s, researchers envisioned that graphite (pure carbon) could be cut into layers measuring only one atom in thickness -- resulting in the material known as graphene.

In the 1990s, researchers managed to create a layer as thin as 100 atoms, but there was no progress after that until 2004, when Russian-born Andre Geim grabbed a tape dispenser from his desk at the University of Manchester, pressed a bit of tape over a thin layer of graphite and peeled it away. When he examined the tape under a microscope, he discovered a layer only one carbon atom thick. Graphene was born!

In 2010, Dr Geim and his colleague, Konstantin Novoselov, were jointly awarded the Nobel Prize in Physics for their work in demonstrating the unique properties of graphene.

Ahead of the pack at NTNU

Six months before Dr Geim and Dr Novoselov arrived in Stockholm to receive their prize, and before graphene had become an item of interest, South Korean post-doctoral fellow Dong Chul Kim at NTNU had suggested to Professors Helge Weman and Bjørn-Ove Fimland at the Department of Electronics and Telecommunications that they should take a closer look at precisely this material. The suggestion came shortly after a research group in their department had succeeded in growing semiconductor nanowires made of gallium arsenide (GaAs) on silicon substrates. This led Dr Weman to wonder if it would be possible to grow semiconductor nanowires directly on graphene instead.

The collective expertise of Professor Weman, Professor Fimland and Dr Kim proved to be a fruitful combination. The researchers quickly achieved their first breakthrough, in September 2010, and in the summer of 2012 they succeeded in placing nanowire semiconductors on a one-atom-thick base. These active semiconductors normally grow to be one micron (a millionth of a metre) in thickness.

Will silicon become obsolete?

Graphene is definitely the hottest topic right now among nanomaterial researchers. The pure-carbon material is by far the thinnest and strongest known to exist. It is 200 times stronger than steel, conducts electricity 100 times faster than silicon and is superior to any other material in conducting heat. It is impenetrable, yet pliable and transparent at the same time. And inexpensive large-scale production of graphene is now becoming a reality.

At present, electronics and solar cells are placed on top of thick silicon substrates. But silicon has clear limitations, including size. Large technology companies are struggling to produce silicon-based products that are smaller than those currently on the market. Another challenge with using silicon is that silicon-based electronics generate a great deal of heat. Many people consider graphene to be the prime candidate for replacing silicon.

Large multinational corporations such as IBM and Samsung have poured a lot of effort into research on both semiconductors and graphene. But the real breakthrough in growing semiconductors on graphene actually took place at NTNU in Trondheim.

The findings of these researchers in Trondheim can be used to make electronics and solar cells that are several hundred times thinner than current models. This will make it possible to produce electronics that are both pliable and transparent, in addition to being less expensive and more energy-efficient.

More efficient solar cells and LEDs

It will probably not be long before simple graphene products begin appearing on the market. Some of them will be based on semiconductor technology.

Semiconductors are a main component in almost all modern electronics. Without them, it would not be possible to have computers, smartphones, solar cells, LED lights or devices using lasers, i.e. everything from printers to fibre communications. All these items can be made smaller and better using graphene. Graphene can both supplant the semiconductor substrate and serve as a transparent electrode for a pliable nanowire solar cell.

"Solar cell and LED technology will be the initial areas to see new products using graphene-based semiconductors," Dr Weman believes.

Under-priced fossil-fuel energy is the primary contributor to global warming. Sunlight is an alternative source with enormous potential, but solar energy will have to become less expensive and more efficient. Semiconductor nanowires based on graphene may just finally tip the scales in favour of solar energy.

"If semiconductor nanowires grown on graphene are used in solar cells, the same amount of sunlight can be converted to energy using one-tenth the volume of materials used in thin-film solar cells. And that means we've cut down on even more material by growing the semiconductors on graphene instead of on a thick semiconductor substrate. New research also shows that graphene has additional unique properties that enhance the efficiency of a solar cell," Dr Weman explains.

LED light bulbs are superior in terms of energy efficiency, but have been more expensive to produce because of costly semiconductor substrates. Semiconductor nanowires on graphene will make it possible to supply the world with LED bulbs that are far cheaper and much more efficient while also being more pliable and weighing less than today's bulbs.

Industrialisation on the horizon

The work on graphene at NTNU has drawn the attention of many international companies interested in collaborating with the Trondheim-based researchers and their company, CrayoNano. But the potential industrial queries so far have come solely from Asia and the US. Actors in Norway and Europe have yet to express any interest.

"We are pioneers in that we are using graphene for something other than basic research. We may already have our first prototype in place by the end of 2013, but we don't wish to reveal what it is yet," Dr Weman says.

"The field we are working with -- using graphene as a replacement for silicon and other semiconductor substrates in electronics and solar cells -- entails many new opportunities. But the potential is just as great for applications using graphene in areas other than electronics, such as in the medical sector. Graphene can be used in the body without causing any harm," Dr Weman explains.

"In a world where drinking water is in short supply, employing oxygen-modified graphene filters to purify water is yet another exciting application. It's a whole new way to turn seawater into fresh water."

In any case, research and development activities will be needed for many years. Dr Weman likens the current state of graphene research to where silicon was in the early 1960s.

Research Council funding paved the way

The Research Council of Norway has been a key source of funding for the Trondheim-based researchers throughout. Helge Weman makes it clear that funding under the Commercialising R&D Results (FORNY2020) programme and the Funding Scheme for Independent Basic Research Projects (FRIPRO) is what made it possible to achieve the unexpected research breakthrough. The researchers have also benefited significantly from funding allocated under the Research Programme on Nanotechnology and New Materials (NANOMAT) and the Large-Scale Programme Clean Energy for the Future (RENERGI).

The professor points out that NTNU's strategic initiative on nanotechnology launched in 2005 is a good example of what future-oriented research policy can help to achieve.

A three-minute video on is available on YouTube in which Helge Weman explains this research: http://www.youtube.com/watch?v=3wLOXHRVVw
Q

Unix/Linux Command Reference

Unix/Linux Command Reference

File Commands

1. ls                         Directory listing

2. ls –al                   Formatted listing with hidden files

3. ls -lt                    Sorting the Formatted listing by time modification

4. cd dir                  Change directory to dir

5. cd                       Change to home directory

6. pwd                    Show current working directory

7. mkdir dir            Creating a directory dir

8. cat >file         Places the standard input into the file

9. more file             Output the contents of the file

10. head file           Output the first 10 lines of the file

11. tail file              Output the last 10 lines of the file

12. tail -f file         Output the contents of file as it grows, starting with the last 10 lines

13. touch file         Create or update file

14. rm file              Deleting the file

15. rm -r dir           Deleting the directory

16. rm -f file           Force to remove the file

17. rm -rf dir           Force to remove the directory dir

18. cp file1 file2     Copy the contents of file1 to file2

19. cp -r dir1 dir2   Copy dir1 to dir2;create dir2 if not present

20. mv file1 file2    Rename or move file1 to file2,if file2 is an existing directory

21. ln -s file            link Create symbolic link link to file

Process management

1. ps                      To display the currently working processes

2. top                     Display all running process Unix/Linux Command Reference

3. kill pid               Kill the process with given pid

4. killall proc         Kill all the process named proc

5. pkill pattern       Will kill all processes matching the pattern

6. bg                      List stopped or background jobs,resume a stopped job in the  background 

7. fg                       Brings the most recent job to foreground

8. fg n                    Brings job n to the foreground

File permission

1. chmod octal file Change the permission of file to octal,which can be found separately for user,group,world by adding,

• 4-read(r)

• 2-write(w)

• 1-execute(x)

Searching

1. grep                        pattern file Search for pattern in file

2. grep -r                    pattern dir Search recursively for pattern in dir

3. command | grep :   pattern  Search pattern in the output of a command

4. locate file               Find all instances of file

5. find . -name           filename Searches in the current directory (represented by

a period) and below it, for files and directories with names starting with filename 

6. pgrep:                    pattern Searches for all the named processes , that matches with the pattern and, by default, returns their ID

System Info

1. date             Show the current date and time

2. cal               Show this month's calender

3. uptime         Show current uptime

4. w                 Display who is on line

5. whoami       Who you are logged in as Unix/Linux Command Reference 6. finger user                             Display information about user

7. uname -a                   Show kernel information

8. cat /proc/cpuinfo       Cpu information

9. cat proc/meminfo     Memory information 

10. man                        command Show the manual for command

11. df                            Show the disk usage

12. du                           Show directory space usage

13. free                         Show memory and swap usage

14. whereis app            Show possible locations of app

15. which app               Show which applications will be run by default

Compression

1. tar cf file.tar file                    Create tar named file.tar containing file

2. tar xf file.tar                          Extract the files from file.tar

3. tar czf file.tar.gz files            Create a tar with Gzip compression

4. tar xzf file.tar.gz                    Extract a tar using Gzip

5. tar cjf file.tar.bz2                   Create tar with Bzip2 compression

6. tar xjf file.tar.bz2                   Extract a tar using Bzip2

7. gzip file                                  Compresses file and renames it to file.gz

8. gzip -d file.gz                         Decompresses file.gz back to file

Unix/Linux Command Reference Shortcuts

1. ctrl+c                   Halts the current command

2. ctrl+z                   Stops the current command, resume with fg in the foreground or bg in                                  the background

3. ctrl+d                   Logout the current session, similar to exit 

4. ctrl+w                  Erases one word in the current line

5. ctrl+u                   Erases the whole line

6. ctrl+r                   Type to bring up a recent command

7. !!                         Repeats the last command

8. exit                      Logout the current session