Advanced Clock Tree Synthesis

Reducing Power with Advanced Clock Tree Synthesis:

Clock trees pose a growing challenge to advanced node IC design, particularly with regard to the chip power consumption. Clocks are the single largest source of dynamic power usage, which makes clock tree synthesis (CTS) and optimization as a good place to achieve significant power savings.

In today’s leading-edge designs, CTS is further complicated by two relatively recent developments: the explosion in the number of modes, corners, and power domains across which the clock must operate, and the increasing resistance and variation in resistance between design corners.

It has become essential to have a power-aware, multi-corner multi-mode (MCMM) CTS with smart clock gate handling, slew shaping, register clumping, and other advanced techniques for reducing power, skew, area, and buffer count.

Multiple Modes, Corners, Power Domains Impact Clock Power:

Variability associated with multiple design modes, process corners, and power states makes balancing clocks more challenging than ever. Using a CTS engine that cannot efficiently and accurately represent more than a couple of mode/corner scenarios leads to errors due to multiple manual CTS runs, longer design times, and lost performance and power because of over-buffering and over-margining required when mode/corner/voltage scenarios are processed serially. 

Process Scaling Effects on Clock Power :

At smaller geometries, resistance per unit length of interconnect is rapidly increasing when compared to capacitance, and if not addressed, could impact circuit performance and clock trees. In addition to the increasing resistance, the variation of these values is also increasing.

Low-Power CTS Techniques:

Clock power consumption is a factor of capacitance, switching activity, and wire length. Low-power CTS strategies include lowering overall capacitance and minimizing switching activity. Some of the advanced techniques to help address power, and also timing, are listed below.

• Reducing functional skew and skew across corners by using MCMM CTS
• Lowering leaf cluster capacitance with register clumping and clock gate cloning and de-cloning
• Improving clock gating coverage with netlist-level gating, hierarchical gating and activity based gating
• Minimizing switching activity with smart clock gate placement