Inputs and Outputs of PD.

Inputs and Outputs at each stage of PD Flow.
Floorplanning:
Inputs:
·    Design Setup
·    Gate Level Netlist
·    Milky way reference Library
·   SDC (Synopsis Design Constraints)
·    TDF (Top Design File)
Outputs:
·         Floorplanned Cell
Checks:
·    Is Macro orientation correct
·    Is placement Legality (i.e. Cell overlaps, cells outside the core boundary ) fine
·   Is Macro placement is according to macro placement guidelines?
·   Placing Macros using Data Flow diagram and by fly-line analysis.

Goal:
·  Goal is to provide continuous area for Standard Cells to be place.
· The Macro plcmt should not lead to Congestion.


Power Planning:
 Inputs:
·         Floor planned Cell
·         Power Budget
·         The top level Engineer may freeze the step , stop, width of Vertical Straps (Because we are designing a block which is going to fit in some chip so the Vertical straps in the chip nd in our block should match, dats the reason In Block level design the top engineer gives us the Vertical straps constraints) {M6pwr.tcl}
Outputs:
·         Power Mesh is Synthesized with IR Drop less than 5 % {VDD+VSS}
·         Floor Planned Cell with Power Mesh
            Checks:
· Check whether u have met the Required IR Drop
· Verify PG connections to check for floating shapes or floating pins  { Power DRC’s }
·Check whether the Placement Legality is fine.

 Goal:
·To meet the Required IR Drop.
If not std cells will not get required power.

 Placement:
 Inputs:
· Floor planned Cell
· Constraints like don’t touch cells (might be already written in SDC ) if not u need to give the cells which u don’t want them to be removed during placement optimization.
· Skew file {in second iteration to meet Timing violations by adding USEFUL SKEW}
Pre requisites for Placement:
·         First of all there should be continuous area for standard cells and the power n/w should be synthesized with the acceptable IR drop.
·        
Checks:
· Check the timing Reports nd analyze them
· Check the Placement Legality
· Check for Global Route Congestion
· Is Std cell Placement Utilization Ok..???

Goal:
· Trying to meet as many setup vio’s as psble.
· Should have acceptable std cell utlzt.
· Should be Congestion Free.

Clock Tree Synthesis:
Inputs:
· Placed Cell
· CTS Constraints
· Non Default Routing Rules {NDR , Bcoz during clock signal (routingclock_route.tcl)Clock nets are largely pruned to Cross Talk effect }

Goal:
·To Balance Insertion Delay
· To make Skew Zero.
For this we this reason we will need to synthesize the clock tree
·After CTS you should meet all the Hold Vio’s.

Checks:
· IS Skew is minimum and Insertion delay balanced.
·IS Timing {Especially Hold} met, if not why?
· If there are timing violations are all the constraints constrained properly.{like not defining false paths, asynchronous paths, multicycle paths}.
· IS std Cell Utilization acceptable at this stage
· Check for Global Route Congestion
· Check for Placement Legality.