Physical Design interview questions

 physical Design interview questions

1. What are the steps involved in designing an optimal pad ring?
2. What are the steps that you have done in the design flow?
3.  What are the issues in floor plan?
4.  How can you estimate area of block?
5. How much aspect ratio should be kept (or have you kept) and what is the utilization?
6.  How to calculate core ring and stripe widths?
7.  What if hot spot found in some area of block? How you tackle this?
8.  After adding stripes also if you have hot spot what to do?
9.  What is threshold voltage? How it affect timing?
10.  What is content of lib, lef, sdc?
11.  What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
12.  In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?
13.  What is ESD?
14. ElectroStaticDischarge. 
15.  What is difference between HFN synthesis and CTS?
16. For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why?
17. What is partial floor plan?
18. What parameters (or aspects) differentiate Chip Design & Block level design??
19. How do you place macros in a full chip design?
20. Differentiate between a Hierarchical Design and flat design?
21. ANs: flat design is design which is designed as a whole.
22. Where as if the design is very big
23. Which is more complicated when u have a 48 MHz and 500 MHz clock design?
24. Name few tools which you used for physical verification?
25. Hercules:  synopsis
26. Caliber:  Menter Graphics.
27. What are the input files will you give for primetime correlation?
28. What are the algorithms used while routing? Will it optimize wire length?
29. How will you decide the Pin location in block level design?
30. If the routing congestion exists between two macros, then what will you do?
31. How will you place the macros?
32. How will you decide the die size?
33. If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
34. If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?
35. In your project what is die size, number of metal layers, technology, foundry, number of clocks?
36. How many macros in your design?
37. What is each macro size and no. of standard cell count?
38. How did u handle the Clock in your design?
39. What are the Input needs for your design?
40. What is SDC constraint file contains?
41. How did you do power planning?
42. How to find total chip power?
43. How to calculate core ring width, macro ring width and strap or trunk width?
44. How to find number of power pad and IO power pads?
45. What are the problems faced related to timing?
46. How did u resolve the setup and hold problem?
47. If in your design 10000 and more numbers of problems come, then what you will do?
48. In which layer do you prefer for clock routing and why?
49. If in your design has reset pin, then it’ll affect input pin or output pin or both?
50. During power analysis, if you are facing IR drop problem, then how did u avoid?
51. Define antenna problem and how did u resolve these problem? 
52. How delays vary with different PVT conditions? Show the graph.
53. Explain the flow of physical design and inputs and outputs for each step in flow.
54. What are delay models and what is the difference between them?
55. What is the significance of negative slack?
56. How the width of metal and number of straps calculated for power and ground?
57. What are clock trees?
58. How slow and fast transition at inputs effect timing for gates?
59.  What is metal density, metal slotting rule?
60. What is OPC, PSM?
61. Why clock is not synthesized in DC?
62. What corner cells contains?
63. What is the difference between core filler cells and metal fillers?
64.  How to decide number of pads in chip level design?