physical design interview questions
what all inputs to the design
SDC,
Netlist.
Physical library,
Technology file,
Tlu+ files
2. what is in logical libraries
timing & functional information.
3. how are values comming into logical libraries
from .lib
4. what are sdcs, how do u decide that a path is a false path?
Sdc
Design rule checks, environmental constraint: pvt disable arcs, false paths, multicycle paths
Optimization constraints: area, power & timing.
5. what is max transition? how you decide that value?
Wherw the slew is worst. Based on top levwl guys experience i.e 20% for data and 10%for clock.
6. How do u set max output load (based on what factors?)
The max_capacitance value can vary with the operating frequency of a cell. (Because the capacitive load vary as per relationship of Xc=1/ωC .)
7. What are the inputs to PT?
Sdc, netlist,
8. How did u do power planning?
9. How did u decide metal 5 straps?
Based on IR drop.
10. Are there in vias between metal 5 and metal 1?
11. Given two configuration of Vdd and Vss; 1. VDD VDD VSS VSS 2. VDD VSS VDD VSS..........which configuration you have used and what does the tool prefer?
Vdd vss because alternative (VDD VSS) will offer better routing resources.
12. Why u require uncertainity before cts with ideal clock?
At pre CTS stage uncertainty is combination of skew, jitter and margin.
To get the better timing at pre CTS.
16. I said -for presenting worst case for setup analysis : then he said he can increase the operating frequency, then y uncertainity is required?
17. What are NDR rules, clock shielding, which metal layer?
Shielding
Double space
double width
top metal layers after power distribution layers.
Because after power clock is the main power hungry.
18. What does u do for low power design?
We apply low power techniques.
Clock gating
Multiple Vt libraries
Multi voltage design
Power gating.
19. What are retention registers?
Retention flops are used in power gating.
To retain the position of the off block when it is turned in.
20. what are HVT cells, how area increases with HVT cells?
For HVT cells the oxide thickness under gate is very high. Such that it can reduces the leakage current. (as oxide thickness increases little area increases)
21. What does CTS do for routing clocks? Global routing..?
22. How global routing is different from detailed routing?
Global routing is first stage of routing which checks for routing congestion of the device.
In track assignment real metal traces are connected to std cells.
23. How GR will handle congested paths, what is its impact on delay?
24. What is single case, worst case and best case and OCV analysis?
25. How can one library have many values for same input slew and output load?
26. What is CRPR? Explain?
27. Logic Design - Difference between flip flops n latch?
28. Convert D into T
29. Get inverter using XOR
Tie one of the input to vdd(logic one).
Now it will work as a inverter.
30. Will you give constraints for via in CTS or not. How vias will effect the clock routing?
Person2:
2. In floorplan what all the factor you have to consider?defining core areas
Perphery area io ports power ports corner cells filler cells
macro placement
Placement blockages
Power network synthesis.
3. Consider you have two macros placed next to each other, what is minimum spacing between the macros?
4. (extension on Q3) u cant over draw any metal layer on the macros and u have macro pins facing the narrow region, what should be the minimum spacing between the macros?
5. What does SDC consist of?
6. How to resolve setup/hold violation after post CTS?
Setup : by lowering the freq
Hold by: working at lowering temperatures.
7. What metal layer you will use for clock routing and why? (top most layer in design is metal7)metal 4 and 5.
8. Useful skew?
9. Cross talk? How to take care of it?
10. Congestion (placement and routing)?
11. Why we will give virtual clock while setting input delay?
Person 3:
1. tell me about torpedo, technology, foundry, clk freq, no. of clk, no of std cells, metal layers, WNS TNS
2. Was your design setup and hold clean if not y?
3. what is setup and hold, what is slack
4. diff latch and ff which has more delay
5. what is SPEF?
6. Measures u took to fix setup and hold?
7. drew buff using xor
8. what is mux ?
9. explain clock gating?
10. in PD flow which was most challenging
11. explain cross talk?
12. explain electronmigration?
13. what isAntenna ratio?
14. how will u reduce IR drop?
15. Given 1000 Hard macros how will u floor plan ?
16. why clock uses NDR.?
Person3:
1. tell me about torpedo, technology, foundry, clk freq, no. of clk, no of std cells, metal layers, WNS TNS
2. was ur design setup and hold clean if not y?
3. what is setup and hold, what is slack
4. diff latch and ff which has more delay
5. what u did in CTS (input files)?
6. Measures u took to fix setup and hold.
7. modes and corners?
8. design a 5x1 mux using 2x1 mux
9. how slew is related to drive strength and delay?
10. in PD flow which was most challenging?
11. cross talk reduction techniques?
12. hold fixing for reg to out path?
13. WC_BC analysis and OCV?
14. how will u reduce IR drop?
15. how u placed ur macros?
16. why clock uses NDR.
17.difference between LVT and HVT cells?
18. how to convert a T flip flop to get same output as input Dff?
Person4:
2)Same design for everyone
3)inputs to your design
4)What are the content of. Lib file..
5)difference b/w normal buff n clkbuf
6)Cross talk
7)What happens if we use cel view instead of fram view.
8)What gate to prefer for clock generation..
8)Congestion n how to overcome
9)How much run time for cts
10)How much time it'll take now
11)Buffer using xor
12)17:1 mux using 2:1 mux
13)Constraints for cts
14)macro placement in floorplan stage
15)Spacing b/w macro
No of pins x metal pitch
Distance between the macros = -------------------------------
(no of metal layers used /2)
16)driving point in your design, data or clock..
17)How Clock uncertainty was introduced
18)How vt of cell is determined
19)Which vt cell to use for hold fixing
20)ndr
21)via b/w m5 n m1..
22)low power design
23)diff b/w latch n ff
24)if 2ns clk is given at high level of 10ns,what is the o/p
Person5:
1)tell me abt yourself
2)what are factor affecting vt
3)how saturation region is different from other two
4)in wt region transistor act as amplifier
5)how do u covert jk to d flip flop?
6)how to obtain inverter from nand
7)explain asic flow ?
8)what are all inputs u 've given to ur design ? inputs at each stage ?
10)what is OCV explain ?
11)inputs given to pt_shell
12)what is .db and lef contains ?
13)how do you give accurate delays to pt_shell , wire load models defined in lib are not accurate ?
14)how to reduce propagation delay ?
15)explain floor plan ?
16)explain placement ?
16)if i 've oly 20 setup violations because of few standard cells and i don wanna go back to floorplan at all wt will be the next thing to do ?
17)after cts what is the next step explain ?
18) if u ve global routing congestion at standard cells how do u reduce it ?
19) layers used in torpedo ?
20)why metal 6 is used t top and why metal 1 is used to prerout ?
21)different path group in your design ?
22)drc to check in pd flow ?
23) is there any inter clock domain in your design?
24)what are all physical drc's ?
25)next step after routing explain ?
26)if i ve critical path due to standard cell how do u reduce after placement ?
27)wr do use separate tool to check lvs ?
28)what is the effect of EM ?
29)can i make skew zero if so what will be the effect ? is there any skew target to ua design?
30)how do u set uncertainity for interclock domain path ?
31)what are all the low power techniques u aware of ?
32)how do you decide location of ports?
33)What are retention registers?
34)explain me negative and positive skew and how r they decided while optimization
these are the questions for which i ve answered sm thing and i forgot few questions
