At Nanometer era of chipdesign physical
verification is palying an important role in gainig the attention of the
Engineer. as the design shrinks a bunch of new Design Rules rules are
creating by the manufacturers for better productivity and yield of the
Chip.
The Main steps in PhysicalVerification
includes
DRC: Design Rule Checks
LVS : Layout Vs Schematic
ERC : Electric Rulr Check
Design Rule Checks:
It verifies
whether the designed layout can be manufactured by the fabrication lab with a
good yield. Here we look after the Physical Design
Rule Violations (DRC), the main errors here we see are Min Spacing
Violation between same Metal layer, Minimum area violation, Min width
Violation, Notch violations, Via Enclosure.
Inputs for DRC at Signoff
Stage:
Design Layout (GDSII)
Design Rule File provided by the fab.
Tools Used for SignOff
DRC: Calibre from
Mentor Graphics, Assura From Cadence , Hercules From Synopsys.
Layout Vs SCHEMATIC:
LVS is also an important step in Physical
Verification, Here we will verifty that the Design Layout (GDSII) is same as
the Netlist (Functionality).
Inputs for LVS:
LVS Rule File
Circuit Level Design Netlist along with IP
(lvs Netlist).
GDSII
LVS is mainly caonsists of 2 steps
Extraction and Comparision.
Here First the Design Netlist is converted
to circuit level transistors, Diodes, Resistors, Capacitors. then GDS is also
converted to its transistor level by extracting These devices are identified in the GDS file by recognition of the
layers and shapes that makes up the circuit or by the cell definition of the
devices/circuits provided in the cell definition file of the intellectual
property blocks or in the LVS rule deck itself, This Process is called
Extraction.
Here mainly we can see
Power (VDD VSS) Connectivity Errors.
Second stage is
comparision Stage after extracting each cell and Net is assigned with a unique
Name and Number respectively in GDS and Netlist, with this unique Nubers and
names tool will compare all cells and Nets and throws an Error if any
Mismatch occurs.
The Main
LVS Erros we observe are
Incorrect
Instances.(Missing Instances).
Incorrect Nets (Shorts,
Opens).
Tools Used for LVS: Calibre from Mentor Graphics.
