quality checks on Netlist

To start the Physical design  these are the files we get input from Synthesis Team.

1)Netlist,

2)SDC.

After receiving database from synthesis team and prior to place and route you can perform some sanity checks. To validate the quality of constraints read in the netlist and the sdc file in the primetime and perform check_timing and generate report which will giving inputs like the quality of database like

how many of the flip flops are getting clocks, 

how many flops are constrained,

how many ports are having constrained or whether there is any violation like that which will surely give some idea about the quality of the delivered database.

In order to understand the quality of the database interms of timing , generate timing reports and understand the quality of timing how good or how bad is the database and how much you can optimize at the backend or at the placement and routing stages or what paths you cannot meet timing even during placement stages

After analying bit on the timing reports you can get some idea of what all areas you need to close pack during placement so that you can create regions.

Generate report_area and report_references -hier report in the designcompiler or synthesis stage to better understand the design hierarchy.

Try performing formal verification using rtl 2 synthesized gates to know whether the design after synthesis stage is meeting formal verification requirement.