What is the difference between the single, bc_wc, and on_chip_variation analysis modes?

What is the difference between the single, bc_wc, and on_chip_variation analysis modes?

Answer:

This article covers the differences between the single, bc_wc, and on_chip_variation analysis modes in PrimeTime. It will also explain how these three analysis modes are affected by the chosen slew propagation mode (worst_slew or worst_arrival).

The following topics are discussed:

·       Two slew propagation modes

·       Timing paths and their proper analysis

·       Three timing analysis modes

·       Potential for optimism in the single and bc_wc analysis modes

It is important to note that DesignTime's min/max mode refers to min and max corners. Hold paths are only checked at the min corner, but on-chip variation within the min corner is included in the analysis. Likewise, setup paths are only checked at the max corner, but on-chip variation within the max corner is included in the analysis.

The three analysis modes can be summarized in the following two charts:

analysis mode	setup launch path	setup capture path
single	slowest path through max-delay arcs, single operating condition, no derating	fastest path through max-delay arcs, single operating condition, no derating
bc_wc	slowest path through max-delay arcs, worst-case operating condition, late derating	fastest path through max-delay arcs, worst-case operating condition, early derating
on_chip_variation	slowest path through max-delay arcs, worst-case operating condition, late derating	fastest path through min-delay arcs, best-case operating condition, early derating

Table 1: Timing Parameters Used For Setup Checks

analysis mode	hold launch path	hold capture path
single	fastest path through max-delay arcs, single operating condition, no derating	slowest path through max-delay arcs, single operating condition, no derating
bc_wc	fastest path through min-delay arcs, best-case operating condition, early derating	slowest path through min-delay arcs, best-case operating condition, late derating
on_chip_variation	fastest path through min-delay arcs, best-case operating condition, early derating	slowest path through max-delay arcs, worst-case operating condition, late derating

Table 2: Timing Parameters Used For Hold Checks