Multi mode multi corner analysis

Multi mode multi corner analysis

 Introduction to MCMM:

Multi-mode multi-corner (MMMC) analysis refers to performing STA across multiple operating modes, PVT corners and parasitic interconnect corners at the same time. For example, consider a DUA that has four operating modes (Normal, Sleep, Scan shift, Jtag), and is being analyzed at three PVT corners (WCS, BCF, WCL) and three parasitic interconnect corners (Typical, Min C, Min RC) as shown in Table 3.1

Pvt corner/ Parasitic corners	WCS	BCF	WCL
Typical	1: Normal/sleep/scan shift/Jtag	2 :Normal/sleep/scan shift	3:Normal/sleep
Min C	4: not required	5:Normal/sleep	6: not required
Min RC	7: not required	8:Normal/sleep	9: not required

Table 3.1: possible scenarios

There are a total of thirty six possible scenarios at which all timing checks, such as setup, hold, slew, and clock gating checks can be performed. Running STA for all thirty six scenarios at the same time can be prohibitive in terms of runtime depending upon the size of the design. It is possible that a scenario may not be necessary as it may be included within another scenario, or a scenario may not be required. For example, the designer may determine

that scenarios 4, 6, 7 and 9 are not relevant and thus are not required. Also, it may not be necessary to run all modes in one corner, such as Scan shift or Jtag modes may not be needed in scenario 5. STA could be run on a single scenario or on multiple scenarios concurrently if multi-mode multicorner capability is available.

What is the difference between the single, bc_wc, and on_chip_variation analysis modes?

What is the difference between the single, bc_wc, and on_chip_variation analysis modes?

Answer:

This article covers the differences between the single, bc_wc, and on_chip_variation analysis modes in PrimeTime. It will also explain how these three analysis modes are affected by the chosen slew propagation mode (worst_slew or worst_arrival).

The following topics are discussed:

·       Two slew propagation modes

·       Timing paths and their proper analysis

·       Three timing analysis modes

·       Potential for optimism in the single and bc_wc analysis modes

It is important to note that DesignTime's min/max mode refers to min and max corners. Hold paths are only checked at the min corner, but on-chip variation within the min corner is included in the analysis. Likewise, setup paths are only checked at the max corner, but on-chip variation within the max corner is included in the analysis.

The three analysis modes can be summarized in the following two charts:

analysis mode	setup launch path	setup capture path
single	slowest path through max-delay arcs, single operating condition, no derating	fastest path through max-delay arcs, single operating condition, no derating
bc_wc	slowest path through max-delay arcs, worst-case operating condition, late derating	fastest path through max-delay arcs, worst-case operating condition, early derating
on_chip_variation	slowest path through max-delay arcs, worst-case operating condition, late derating	fastest path through min-delay arcs, best-case operating condition, early derating

Table 1: Timing Parameters Used For Setup Checks

analysis mode	hold launch path	hold capture path
single	fastest path through max-delay arcs, single operating condition, no derating	slowest path through max-delay arcs, single operating condition, no derating
bc_wc	fastest path through min-delay arcs, best-case operating condition, early derating	slowest path through min-delay arcs, best-case operating condition, late derating
on_chip_variation	fastest path through min-delay arcs, best-case operating condition, early derating	slowest path through max-delay arcs, worst-case operating condition, late derating

Table 2: Timing Parameters Used For Hold Checks