DIFFERENCE BETWEEN DIBL AND GIDL.

GIDL:  gate induced drain leakage is a leakage mechanism from the gate-drain overlap region caused when the Drain voltage is very high and Gate voltage is very low.The reverse biased pn junction will undergo band to band tunneling in which the electrons tunnel from the valence band of the n-type tunnel into the conduction band of the p-type and the holes tunnel vice-verse. This results in a leakage current through the gate oxide.

DIBL: Drain induced barrier lowering is related to the reduction in the threshold voltage of the transistor due to the large depletion region created by the Drain potential.U can think of it as-since already a part of the region under the gate is depleted by the drain, only a little amount of gate potential is needed to complete depletion in the rest of the area.This means a lower threshold voltage.

Rectangular FINS VS Triangular FINS

On 23^th April Chipworks posted a blog revealing the inner workings of the Intel 22 nm technology and the architecture of the corresponding FinFETs or, as Intel calls them, tri-gate transistors.

Figs 5, 6 and 7 in the Chipworks posting compare the “unexpected” slope of the fabricated transistors with the original tri-gate schematic shown by Intel last year. There is a lot of speculation about the possible advantages and disadvantages of the trapezoidal (or almost triangular) shaped ‘bulk’ FinFET.

Driven by natural curiosity we decided to shine some light on these questions by doing 3D simulations with our ‘atomisic’ simulatorGARAND, although at this initial stage the ‘atomicity’ doesn’t play any role in our simulations. Fig 1 compares the TEM image of one of the FinFETs from Fig. 7 of the Chipworks posting with our simulation domain. Since we do not have information about the doping distribution in the Intel FinFETs we have assumed a lightly doped channel, which is beneficial from the point of view of statistical variability.

Fig. 1 Comparison of the TEM image of one of the FinFETs from Fig. 6 of the Chipworks blog with the GARAND simulation domain.

The electron concentration and the potential distribution along the fin are illustrated in Fig.2. We have assumed that there is a high doping concentration stopper below the fin in the STI region. Clearly FinFETs are more complicated devices in terms of understanding and visualisation compared to the ‘old’ bulk MOSFETs.

Fig. 2 Electron concentration and the potential distribution along the fin.

The current density distribution across the fin in the middle of the channel at different gate bias conditions is illustrated in Fig. 3 and is rather complex. At low gate voltage the maximum current density is in the middle of the channel where the gate has least control over the turning-off of the device. The depletion region caused by the highly-doped stopper below the channel prevents current flow at the very bottom of the channel – one drawback of the bulk FinFET architecture. At high gate voltage the current moves towards the interface, crowding at the top of the fin due to the focusing gate fringing field there, with quantum mechanical confinement concentrating the charge in a small circular region. Fig. 4 animates the changing gate bias, focussing on the fin channel.

Fig. 3 Current density distribution across the Fin at different gate bias conditions.

Fig. 4. Close-up view of the fin with an animation of the current density with increasing gate bias.

Undoubtedly the result that we found most interesting is the comparison in Fig. 5 between the gate length dependence of the threshold voltage for the trapezoidal Intel transistor and an equivalent rectangular-fin transistor (same fin height and with fin width equal to the average width of the trapezoidal fin). Clearly the rectangular fin has better short channel effects. Still, the million dollar question is if the almost-triangular shape is ‘on purpose’ design, or is this what bulk FinFET technology can achieve in terms of the fin etching?

Fig. 5 Threshold voltage dependence on gate length comparing the Intel-type structure with an ideal rectangular FinFET.

We would be delighted to hear your opinions on this interesting device, particularly with regard to the shape.

9 track cells VS 12 track cells

track is defined as the path in which nets can pass through.

Track is generally used as a unit to define the height of the std cell. a 12 track cell will  be taller than a 9 track cell. a 12 track std cell will be taller , that means more metal 1 routing  space is available within the cell, hence cells will be faster. where as in a 9 track cell, the cell  will be compact, but speed is less compared to 12 track.

9track, less area, less speed compared to 12 track.

12tarck, more area, more speed compared to 9 tracks.

Wide performance range for all types of designs

• Ultra high density/low power; 7 or 8-track (SC7/SC8) libraries for cost critical applications.

• High density; 9 or 10-track (SC9/SC10) libraries for mainstream applications.

• High performance; 12-track (SC12) libraries for speed critical designs.

• Variety of architectures based on different track heights and cell designs cover a wide performance, power and area range.
• High Performance libraries are 20% faster than High Density mainstream libraries
• Ultra High Density versions based on smallest cell height require 20% less area and power than mainstream libraries.

FINFETS

WHY FINFETS

                                        Since the advent of semiconductors and throughout the long history of designing integrated circuits for everything from computer hardware to multifunction mobile devices, the basic tenet of Moore's law has remained the same: the number of transistors on a given area of silicon doubles every two years.

Between the foundries developing advanced process nodes and their consumers' insatiable demand for more functionality, the industry has fulfilled Moore's Law. The transistor count on today's advanced multicore processors is reaching the 3billion range – a long way from the 6800 processor of the mid 1970s that had just 5000 transistors.

Semiconductor manufacturing foundries helped make this growth achievable by introducing smaller geometry cmos process nodes using planar field effect transistor (FET) technology, where the latest node effectively doubled the gate density compared to the previous generation every couple of years. As we approached the sub nanometre range with the 90nm node and beyond, static leakage became an important factor such that while every new process generation may have doubled the gate density, it also doubled the amount of leakage current.

This leakage could be mitigated through the use of high voltage threshold dopants at the expense of device performance, or through the use of advanced design techniques, such as power gating or multivoltage islands. Controlling current leakage when the transistors are switched off is important to preserve battery life or minimise power consumption in computer and mobile applications that spend most of their time in an idle state.

Economics also plays a factor in determining whether to move to advanced processes and when. If chips can take advantage of the increased density to provide more functionality, then it generally made sense to move to the next node, even if mask and process costs were higher. This was the case as designs moved from 65nm to 45/40nm and then again to 28nm. However, the 20nm process node has introduced a new set of challenges, including double patterning and very leaky transistors due to short channel effects. Both are negating the benefits of transistor scaling.

The move from 28nm to 20nm was also unattractive economically for many, since it didn't provide the same level of performance and area gains seen with previous generations. Even with the 30 to 50% density improvement enabled by moving from the 28nm to 20nm process technologies, the performance gain is nowhere near the same as that seen with the move from the 45/40nm to the 28nm process node.

While the planar FET may have reached the end of its scalable lifespan, the semiconductor industry has found an alternative approach with FinFETs; viewed by many as the best choice for next generation advanced processes.

With advanced geometry planar FET technologies, such as 20nm, the source and the drain encroach into the channel, making it easier for leakage current to flow between them and making it very difficult to turn the transistor off completely (see fig 1a). FinFETs are 3d structures that rise above the substrate and resemble a fin, hence the name. The 'fins' form the source and drain, effectively providing more volume than a planar transistor for the same area (see fig 1). The gate wraps around the fin, providing better control of the channel and allowing very little current to leak through the body when the device is in the 'off' state. This, in turn, enables the use of lower threshold voltages and results in better performance and power.



Many semiconductor design companies are moving rapidly to manufacturing their devices on the advanced 16nm and 14nm FinFET based process geometries, simply because the performance and power benefits are compelling. Many test chips have taped out and the results are now starting to come in.

One of the earliest manufacturing providers at the 14nm process node, Samsung has been developing FinFET process technology for several years and is now ready for early adopter production. Samsung's 14nm LPE process is providing almost 150% better performance from a die half the size of the previous node and improving power consumption by around 150% when compared to its 28nm process technology (see fig 2).




From the economic perspective, data from International Business Strategies shows that the move to 20nm and FinFET results in essentially the same cost per die (Q1 2014 estimates), especially as devices increase in size (see fig 3).



FinFET devices can operate from a lower supply voltage than planar transistors since they have a lower threshold voltage. This drop in supply voltage can improve dynamic power consumption significantly: at the least, users can expect a 20% improvement from a drop in supply voltage of just 0.1V and this constitutes a strong driver for FinFET adoption.

Given that the transistors can operate at a much lower voltage than nominal, additional dynamic power savings on that facet alone would be achievable. In addition, foundation library providers are investigating whether or not it makes sense to introduce smaller height standard cells that could reduce dynamic power consumption further.

These providers are likely to release different height libraries, allowing designers to target specific performance or power applications as foundry process design kits are stabilising for production.

FinFET processes are already in production. Intel was one of the first semiconductor manufacturers to use the 22nm node, where it reported power savings of up to 50% when compared to its 32nm process. Semiconductor manufacturers such as TSMC, Samsung Foundry and GlobalFoundries are also moving to production rapidly with several test chips already taped out. But what does it take to move a design to the new FinFET processes and take advantage of the performance and power benefits?

The 20nm process node was necessary to help build the foundation for the advanced FinFET processes. With the smaller device geometries, traditional lithography/optical manufacturing techniques no longer have the required resolution where double patterning – using litho-etch-litho processing – becomes necessary. The number of manufacturing design rules has increased significantly and these have to be handled by various eda tools, such as place and route, physical verification and extraction.

The industry's experience with 20nm has paved the way for an easier transition to FinFET processes. Many of the tool improvements can still be applied, but the handling of FinFETs does require a few more changes; for example, SPICE BSIM-CMG models had to be created to add the 3d effects. It is also true that, with 3d transistors, capacitance becomes a primary concern. EDA tools must build in high resistance interconnect optimisation in order to mitigate these capacitive effects. Layer awareness is also essential to provide optimal metal layer assignment during routing of the design.

Although FinFET processes may seem new, development of the technology itself has been in progress for almost a decade. The industry has worked together to make the shift to an advanced new process node as seamless as possible, with minimal impact to current design methodologies.

Consumer appetite for new functionality remains high and the move to designing with FinFET process technologies will help fill that need and keep Moore's Law very much alive.

Mary Ann White is product marketing director, Galaxy Implementation Platform, for Synopsys.

Author
Mary Ann White