Advanced Clock Tree Synthesis

Reducing Power with Advanced Clock Tree Synthesis:

Clock trees pose a growing challenge to advanced node IC design, particularly with regard to the chip power consumption. Clocks are the single largest source of dynamic power usage, which makes clock tree synthesis (CTS) and optimization as a good place to achieve significant power savings.

In today’s leading-edge designs, CTS is further complicated by two relatively recent developments: the explosion in the number of modes, corners, and power domains across which the clock must operate, and the increasing resistance and variation in resistance between design corners.

It has become essential to have a power-aware, multi-corner multi-mode (MCMM) CTS with smart clock gate handling, slew shaping, register clumping, and other advanced techniques for reducing power, skew, area, and buffer count.

Multiple Modes, Corners, Power Domains Impact Clock Power:

Variability associated with multiple design modes, process corners, and power states makes balancing clocks more challenging than ever. Using a CTS engine that cannot efficiently and accurately represent more than a couple of mode/corner scenarios leads to errors due to multiple manual CTS runs, longer design times, and lost performance and power because of over-buffering and over-margining required when mode/corner/voltage scenarios are processed serially. 

Process Scaling Effects on Clock Power :

At smaller geometries, resistance per unit length of interconnect is rapidly increasing when compared to capacitance, and if not addressed, could impact circuit performance and clock trees. In addition to the increasing resistance, the variation of these values is also increasing.

Low-Power CTS Techniques:

Clock power consumption is a factor of capacitance, switching activity, and wire length. Low-power CTS strategies include lowering overall capacitance and minimizing switching activity. Some of the advanced techniques to help address power, and also timing, are listed below.

• Reducing functional skew and skew across corners by using MCMM CTS
• Lowering leaf cluster capacitance with register clumping and clock gate cloning and de-cloning
• Improving clock gating coverage with netlist-level gating, hierarchical gating and activity based gating
• Minimizing switching activity with smart clock gate placement

WHY SCAN FREQUENCY SHOULD BE LOWER THAN CLOCK FREQUENCY?

why scan frequency should be low?

                During Testing Circuit activity increases during testing and leads to high test power dissipation. i.e

Drop in power supply voltage due to IR drop

Drop in voltage lowers current flowing through transistor

Time taken to charge load capacitor increases.

Causes

  Ground bounce

  Excessive heating ,Permanent damage in circuit

  Good chip labeled bad, unnecessary yield loss

  stuck and delay faults

Clock Speed-Up under Power Constraints

Test clock frequency lowered to reduce power dissipation

Power dissipated in a clock cycle, ½ CV ²œ  (œ= switching power)

Worst case power =½ CV ²œ _{peak    = power budget.}

  F _test <= (2 * powerbudget) / CV ²œ _peak    >=  (½)CV ²œ _peak F _test

If œ =  œ _peak/ I    then    f= i * ftest without exceeding Pbudget

C, V constant for a circuit

Test clock can be increased when switching activity is low

Strong correlation between number of transitions in scan cells and test power dissipation.

Low activity in scan chain => Scan frequency can be increased without exceeding Pbudget .

why clock inverters over clock buffers?

why clock inverters  over clock buffers?

The factors which we consider are the equal rise time  and fall time, drive strength and the insertion delay of the cell. a perfect clock tree is that which have equal rise and fall times with 50% duty cycle for the clock. comparatively clock inverters will have less delay than buffers of same drive strength, also inverters. 

    If we replace a buffer with 2 inverter we can balance the clock rise and fall delay for longer length of the net.  

FD-SOI

Introduction to FD-SOI:

                              Fully-Depleted Silicon On Insulator, FD-SOI, is emerging as a promising  solution to continue the CMOS scaling roadmap at the 22nm technology node and beyond, especially for Low Power and System-on-Chip applications. 

                          Compelling simulation and silicon data for nanometer scale transistors is becoming available. However, as potential users realize the many interests of this technology, the next question is: what about design ? Would a  transition to a Fully-Depleted SOI technology mean a lot of disruption at design level? With FD-SOI processes for the 22nm/20nm CMOS node still in demonstration phase, it is early to give complete answers; on the other hand, this is an important factor in the decision to fully engage in this technology, so it is worth sketching the best picture possible at this stage. This document therefore intends to synthesize what is known or can be most reasonably expected when designing for FD-SOI; it will also indicate some new potentialities opened up by FD-SOI that designers may be able exploit. It builds upon information released in publications such as those listed at the end of  this document or workshops organized by the SOI Consortium.

                          It hopes to demonstrate that a transition to FD-SOI could be, to a large extent, a continuation of current design  practices rather than a revolution, with some added benefits for designers. After a quick overview of the FD-SOI technology and the opportunities it offers, this review will address its impact  on design from System-on-Chip integration level, through complex IP level, down to foundation IP and library design level.

Unique Features of FD-SOI:

Figure shows how a few unique features of FD-SOI namely the absence of channel doping, the ultra-thin body, the resulting excellent electrostatic control of the channel, plus the total substrate isolation enable devices that can be used very advantageously from a design and product perspective for low power System on Chip. 

SHORT CUTS FOR EDITING WIRES IN CADENCE 14.1

Short cuts for editing wires in cadence 14.1

E	Opens or closes the Edit Route form
A	Select
Shift+A	Edit Wire
M	Move Wire
O	Add Via
S	Stretch Wire
Shift+X	Cut Wire
Shift+R	Move/Resize/Reshape (non-connectivity-based move/resize/stretch)
Shift+S	Populates the Edit Route form with net name, width, layers, and shape of highlighted (queried) wire or pin.
P	Toggles to previous object under cursor.
D	Opens or closes the Select/Delete/Deselect Route form
N	Toggles to next object under cursor.
Ctrl+W	Deletes the queried segment or via.
Esc	Removes the entire route.
Number keys	Change the added wire to a specific layer number. If you want the wire to be added to metal layer 1, use the 1 keyboard shortcut, use the 2 keyboard shortcut for metal layer 2, and so forth.
Single-click	Ends the segment, allowing you to continue the route in either the same direction or the orthogonal direction.
Double-click	Ends the route.
D	Changes the added wire to the layer below the current layer.
U	Changes the added wire to the layer above the current layer.

Inputs and Outputs of PD.

Inputs and Outputs at each stage of PD Flow.
Floorplanning:
Inputs:
·    Design Setup
·    Gate Level Netlist
·    Milky way reference Library
·   SDC (Synopsis Design Constraints)
·    TDF (Top Design File)
Outputs:
·         Floorplanned Cell
Checks:
·    Is Macro orientation correct
·    Is placement Legality (i.e. Cell overlaps, cells outside the core boundary ) fine
·   Is Macro placement is according to macro placement guidelines?
·   Placing Macros using Data Flow diagram and by fly-line analysis.

Goal:
·  Goal is to provide continuous area for Standard Cells to be place.
· The Macro plcmt should not lead to Congestion.


Power Planning:
 Inputs:
·         Floor planned Cell
·         Power Budget
·         The top level Engineer may freeze the step , stop, width of Vertical Straps (Because we are designing a block which is going to fit in some chip so the Vertical straps in the chip nd in our block should match, dats the reason In Block level design the top engineer gives us the Vertical straps constraints) {M6pwr.tcl}
Outputs:
·         Power Mesh is Synthesized with IR Drop less than 5 % {VDD+VSS}
·         Floor Planned Cell with Power Mesh
            Checks:
· Check whether u have met the Required IR Drop
· Verify PG connections to check for floating shapes or floating pins  { Power DRC’s }
·Check whether the Placement Legality is fine.

 Goal:
·To meet the Required IR Drop.
If not std cells will not get required power.

 Placement:
 Inputs:
· Floor planned Cell
· Constraints like don’t touch cells (might be already written in SDC ) if not u need to give the cells which u don’t want them to be removed during placement optimization.
· Skew file {in second iteration to meet Timing violations by adding USEFUL SKEW}
Pre requisites for Placement:
·         First of all there should be continuous area for standard cells and the power n/w should be synthesized with the acceptable IR drop.
·        
Checks:
· Check the timing Reports nd analyze them
· Check the Placement Legality
· Check for Global Route Congestion
· Is Std cell Placement Utilization Ok..???

Goal:
· Trying to meet as many setup vio’s as psble.
· Should have acceptable std cell utlzt.
· Should be Congestion Free.

Clock Tree Synthesis:
Inputs:
· Placed Cell
· CTS Constraints
· Non Default Routing Rules {NDR , Bcoz during clock signal (routingclock_route.tcl)Clock nets are largely pruned to Cross Talk effect }

Goal:
·To Balance Insertion Delay
· To make Skew Zero.
For this we this reason we will need to synthesize the clock tree
·After CTS you should meet all the Hold Vio’s.

Checks:
· IS Skew is minimum and Insertion delay balanced.
·IS Timing {Especially Hold} met, if not why?
· If there are timing violations are all the constraints constrained properly.{like not defining false paths, asynchronous paths, multicycle paths}.
· IS std Cell Utilization acceptable at this stage
· Check for Global Route Congestion
· Check for Placement Legality.