Introduction to FD-SOI:
Fully-Depleted Silicon On Insulator, FD-SOI, is emerging as a promising solution to continue the CMOS scaling roadmap at the 22nm technology node and beyond, especially for Low Power and System-on-Chip applications.
Compelling simulation and silicon data for
nanometer scale transistors is becoming available. However, as potential users
realize the many interests of this technology, the next question is: what about
design ? Would a transition to a Fully-Depleted SOI technology mean a lot
of disruption at design level? With FD-SOI processes for the 22nm/20nm CMOS
node still in demonstration phase, it is early to give complete answers; on the
other hand, this is an important factor in the decision to fully engage in this
technology, so it is worth sketching the best picture possible at this stage.
This document therefore intends to synthesize what is known or can be most
reasonably expected when designing for FD-SOI; it will also indicate some new
potentialities opened up by FD-SOI that designers may be able exploit. It
builds upon information released in publications such as those listed at the
end of this document or workshops organized by the SOI Consortium.
It hopes to demonstrate that a transition
to FD-SOI could be, to a large extent, a continuation of current design
practices rather than a revolution, with some added benefits for
designers. After a quick overview of the FD-SOI technology and the
opportunities it offers, this review will address its impact on design
from System-on-Chip integration level, through complex IP level, down to
foundation IP and library design level.
Unique Features of FD-SOI:
Figure shows how a few unique features of FD-SOI namely the absence of channel doping, the ultra-thin body, the resulting excellent electrostatic control of the channel, plus the total substrate isolation enable devices that can be used very advantageously from a design and product perspective for low power System on Chip.
Figure shows how a few unique features of FD-SOI namely the absence of channel doping, the ultra-thin body, the resulting excellent electrostatic control of the channel, plus the total substrate isolation enable devices that can be used very advantageously from a design and product perspective for low power System on Chip.
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